1. Field of the Invention
The invention relates to the field of embedded processor architecture and more particularly to multithreaded central processing units (CPUs).
2. Description of Background Art
Conventional embedded processors, e.g., microcontrollers, support only a single hard real-time asynchronous process since they can only respond to a single interrupt at a time. Most software implementations of hardware functions-called virtual peripherals (VPs)—respond asynchronously and thus their interrupts are asynchronous. Some examples of VPs include an Ethernet peripheral (e.g., 100 Mbit and 10 Mbit Transmit and receive rates); High-speed serial standards peripherals, e.g., 12 Mbps universal serial bus (USB), IEEE-1394 Firewire Voice Processing and Compression: ADPCM, G.729, Acoustical Echo Cancellation (AEC); an image processing peripheral; a modem; a wireless peripheral, e.g., an IRDA (1.5 and 4 Mbps), and Bluetooth compatible system. These VPs can be used as part of a home programmable network access (PNA) system, a voice over internet protocol (VoIP) system, and various digital subscriber line systems, e.g., asymmetric digital subscriber line (ADSL), as well as traditional embedded system applications such as machine control.
An embedded processor is a processor that is used for specific functions. Embedded processors generally have some memory and peripheral functions integrated on-chip. Conventional embedded processors have not been capable of operating using multiple hardware threads.
A pipelined processor is a processor that begins executing a second instruction before the first instruction has completed execution. That is, several instructions are in a “pipeline” simultaneously, each at a different stage. FIG. 1 is an illustration of a conventional pipeline.
The fetch stage (F) fetches instructions from memory, usually one instruction is fetched per cycle. The decode stage (D) reveals the instruction function to be performed and identifies the resources needed. Resources include general-purpose registers, buses, and functional units. The issue stage (I) reserves resources. For example, pipeline control interlocks are maintained at this stage. The operands are also read from registers during the issue stage. The instructions are executed in one of potentially several execute stages (E). The last writeback stage (W) is used to write results into registers.
One example of a non-conventional multithreaded processor is described in U.S. patent application Ser. No. 09/748,098 that is referenced above, that enables each stage of the pipeline to be processing a thread that is different from the thread in either the preceding or following stage. This permits the multithreaded processor to interleave the processing of multiple threads which permits the timely processing of time-critical applications and interrupts, for example.
A problem with conventional multithreaded processors is that each thread has a separate hardware state for each thread. This hardware state may be in the form of separate sets of registers. However, in normal operation such conventional systems permit each thread access only to its own set of state registers, i.e., its own state. There is no ability to use or alter the characteristics of other states. This restriction limits the ability for a particular thread to take control of the system and to initialize a thread while other threads are still operating, for example.
What is needed is a system and method that (1) enables a thread in a multithreaded processing environment to access states of other threads and; (2) enables a thread to store states of other threads.